BiSn-Based Low-Temperature Soldering Process and Reliability, Phases 1-3a

Statement of Work & Project Statement

Statement of Work (Version 1.4; December 1, 2015)
Project Statement (Version 1.4; December 1, 2015)

Background

There have been drivers from most ODMs and some OEMs to adopt low-temperature soldering for the assembly of consumer electronic products, such as cell phones, tablets and mobile computers. The motivations for these drivers have been threefold: environmental, economic and technical.

Solders in the BiSn system, particularly compositions close to the eutectic (58wt% Bi), are prone to brittle fractures at high strain rates. This leads to a high risk of brittle fracture of BiSn-based solder joints under mechanical shock and drop conditions for electronic products. To mitigate this risk, solder paste manufacturers have explored two pathways. One is through the development of a more ductile metallurgy within the BiSn solder system by reductions of the bismuth content and addition of elemental dopants, both of which enhance the solder bulk mechanical properties by modifying its microstructure. The other is through the incorporation of polymer resins in the solder paste that, during the reflow soldering process, cures after the solder wets to the metallic surfaces of the board and the component, and forms a polymeric reinforcement around the solder joint after the assembly cools down. There is very little independent assessment of these two pathways, both in terms of the processibility of these new solder pastes and the reliability of the solder joints thus formed by their use.

Objective

The purpose of this project is to assess the surface mount processibility and reliability of the solder joints formed when enhanced BiSn-based solder pastes are used for assembling electronic components on printed circuit boards.

Presentations

“Thermal Cycling Hybrid, Homogeneous, and Resin Reinforced Low Temperature Solder Ball Grid Array Interconnects at a High Homologous Temperature,” presented by Richard Coyle, PhD, Nokia Bell Labs, LTS1: Thermal Fatigue and Mechanical Shock Reliability of LTS Solder Joints. Originally published in the Proceedings of the SMTA International, pp 223-239 (October 20-24, 2024, Rosemont, Illinois USA). NOTE: This paper received an honorable mention in the “Best of Proceedings” awards from SMTA.
The Effect of Thermal Cycling Profile on Thermal Fatigue Performance of an 84-Pin Thin Core BGA with Hybrid, Homogeneous, and Resin Reinforced Low Temperature Solder Interconnects, Dan Burkholder and Raiyo Aspandiar, Ph.D., Intel Corporation; presented by Raiyo Aspandiar, SMTA International 2023, Session LTS1: Thermal Cycling Performance of LT Sn-Bi Solder Joints with and without Aging Low Temperature Solder, October 11, 2023; Minneapolis, Minnesota. (Originally published in the proceedings of the SMTA International, October 9 - October 12, 2023)
The Effect of Thermal Cycling Profile on Thermal Fatigue Performance of a 192-Pin Chip Array BGA with Hybrid, Homogeneous, and Resin Reinforced Low Temperature Solder Interconnects,”presented by Dan Burkholder, Intel Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology, Phase 2 paper presentation Proceedings of the SMTA International, October 31-November 3, 2022
Thermal Cycling Performance of Hybrid, Homogenous and Resin Reinforced Low Temperature Solder Ball Grid Array Interconnects,” presented by Richard Coyle, Nokia Bell Labs paper presentation Originally published in the Proceedings of the SMTA International, October 31-November 3, 2022
Interim Thermal Cycling Report on Hybrid and Homogeneous LTS Solder Joints,” Richard Coyle, Ph.D. (Nokia Bell Labs), Session LTS2: Reliability Testing, SMTA International, November 2, 2021 (Minneapolis, Minnesota) paper presentation
The Surface Mount Technology Association (SMTA) recognized this paper with a Best of Proceedings Paper Award for the 2021 SMTA International conference.
Mechanical Shock Testing and Failure Analysis on Mixed SnAgCu-BiSn and Full Stack BiSn Solder Joints of CABGA192 Components," Jagadeesh Radhakrishnan (Intel), Session LTS2: Reliability Testing, SMTA International, November 2, 2021 (Minneapolis, Minnesota). paper presentation
This paper received an honorable mention as part of the Surface Mount Technology Association’s Best of Proceedings Paper Award for the 2021 SMTA International conference.
Mechanical Shock Performance of LTS,” Raiyo Aspandiar and Jagadeesh Radhakrishnan (Intel), INEMI Board Assembly Tech Topic Series Webinar, September 21 & October 12, 2021
Post Mechanical Shock Failure Analysis on Mixed BGA-SAC Solder Joints of POP Components, presented by Raiyo Aspandiar (Intel Corporation), SMTA Pan Pacific Microelectronics Symposium (February 13; Kauai, Hawaii)
Post Mechanical Shock Test Failure Analysis on Mixed SnAgCu-BiSn BGA Solder Joints,” Raiyo Aspandiar (Intel), On-Demand Session OD-49, ICEP 2021 (virtual event)
Mechanical Shock Testing and Failure Analysis on Mixed SnAgCu-BiSn and Full Stack BiSn Solder Joints of CABGA192 Components,” Raiyo Aspandiar, Ph.D., and Jagadeesh Radhakrishnan (Intel Corporation), Session LTS2: Reliability Testing, SMTA International, November 2, 2021 (Minneapolis, Minnesota) paper presentation
INEMI Project on Process Development of BiSn-Based Low Temperature Solder Pastes - Part VII: Mechanical Shock Test and Failure Analysis on Mixed SnAgCu-BiSn Solder Joints of FCBGA Components, Presentation #462: Lead-Free & Low Temp Soldering Technologies (LF) Track, presented by Jagadeesh Radhakrishnan (Intel), SMTA International 2020. paper presentation
INEMI Project on Process Development of BiSn-Based Low Temperature Solder Pastes Part VI: Post Mechanical Shock Failure Analysis on Mixed SnAgCu-BiSn Solder Joints of FCBGA Components, presented by Raiyo Aspandiar (Intel Corporation), SMTA International, September 26, 2019; Rosemont, Illinois.
INEMI Project on Process Development of BiSn-Based Low Temperature Solder Pastes Part IV: Comprehensive Mechanical Shock Tests on POP Components Having Mixed BGA BiSn-SAC Solder Joints; presented by Raiyo Aspandiar (Intel), SMTA International, October 18, 2018 (Rosemont, Illinois) paper presentation
Presentation and Paper: INEMI Project on Process Development of BiSn-Based Low Temperature Solder Pastes Part III: mechanical shock tests on PoP BGA assemblies, Jagadeesh Radhakrishna (Intel), presented at ICEP-IAAC 2018 (April 19, 2018; Kuwana, Mie, Japan) (INEMI members only)
INEMI Project on Process Development of BiSn-Based Low-Temperature Solder Pastes - Part II: Characterization of Mixed Alloy BGA Solder Joints; Raiyo Aspandiar (Intel); Pan Pacific Microelectronics Symposium (February 6, 2018; Big Island, Hawaii) paper presentation
INEMI Project on Process Development of BiSn-Based Low-Temperature Solder Pastes; Raiyo Aspandiar (Intel); SMTAI (September 20, 2017; Rosemont, Illinois, USA) paper presentation

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BiSn-Based Low-Temperature Soldering Process and Reliability, Phases 1-3a

Statement of Work & Project Statement

Background

Objective

Presentations

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